1. Field of the Invention
The present invention relates to a logic circuit and particularly to a bulk input differential logic circuit with fewer circuit elements for a complicated logic and high speed operation.
2. Description of the Prior Art
FIG. 1 is a diagram showing a static CMOS circuit of a 3-input NOR gate. It includes three P-type transistors 111, 112 and 113 having gates receiving signals A, B and C respectively, and three N-type transistors 121, 122 and 123 connected in parallel having gates receiving the signals A, B and C respectively. One of the N-type transistors 121, 122 and 123 is turned on and a logic Low is output on the terminal Vo if one of the signals A, B, and C carries a logic High. All of the P-type transistors 111, 112 and 113 are turned on and a logic High is output on the terminal Vo if all of the signals A, B, and C carry a logic Low. This circuit has an advantage in that there is no DC power consumption. However, it has a disadvantage in that 2n transistors are needed to implement a n-input NOR gate. The input capacitor of this circuit equals a sum of the gate capacitors of the P-type and N-type transistors. Thus, the circuit will operate at a relatively low speed if the number of the inputs is large.
FIG. 2 is a diagram showing a conventional dynamic CMOS circuit of a logic gate. It includes a P-type transistor 211 and a N-type transistor 212 having gates commonly coupled to receive a clock signal φ, and four transistors 221, 222, 223 and 224 having gates coupled to receive signals A, B, and their inverted signals A′ and B′ respectively. During a pre-charge period when the clock signal φ is at the logic Low, the transistor 211 is turned on and the logic High is output on the terminal Vo. During an evaluation period when the clock signal φ is at the logic High, the transistors 221, 222, 223 and 224 are turned on or off in response to the signals A and B. A current path from the terminal Vo to the ground is formed and the logic Low is output on the terminal Vo when both of the signals A and B carry the logic High or Low. Otherwise, the logic High is output on the terminal Vo. Thus, it operates as a logic function of Vo=AB+A′B′. Only (n+2) transistors are needed to implement a n-input logic gate. The can operate at a high speed even if the number of the inputs is large. However, it is possible that the terminal Vo floats under certain situations.
FIG. 3 is a diagram showing a conventional transmission gate. It includes P-type transistor 31 and N-type transistor 32. The gates of the transistors 31 and 32 respectively receive a signal B and its inverted signal B′ and the source and drain of the transistors 31 and 32 are commonly coupled to receive another signal A and as an output terminal Vo. When the signal B carries the logic High, the terminal Vo is electrically connected to output the signal A. When the signal B carries the logic Low, the terminal Vo floats. Thus, the signal B acts as a switch control signal determining whether the signal A is transmitted to the terminal Vo. This circuit has a lower resistance but higher capacitance than those of the static CMOS circuit. The most serious problem with this circuit is that the terminal Vo is not biased by a DC voltage, which may result in wrong output due to power consumption in transmission.
FIG. 4 is a diagram showing a logic circuit using a differential cascade voltage switch (DCVS) disclosed in U.S. Pat. No. 4,570,084. It includes four P-type transistors 411, 412, 421 and 422, inverters 431 and 432, NMOS differential logic tree 44, and a N-type transistor 45. During a pre-charge period when the clock signal φ is at the logic Low, the transistors 412 and 421 are turned on and the logic High is output on the terminals Q and Q′. During an evaluation period when the clock signal φ is at the logic High, the NMOS differential logic tree 44 provides only current path to the ground, whereby one of the voltage levels on the terminals Q and Q′ is pulled down to the logic Low. For example, the only current path provided by the NMOS differential tree 44 is from the terminal Q to the ground. The voltage level on the terminal F′ is pulled up so that the N-type transistor 422 is turned on. This also helps to pull down the voltage level on the terminal Q to the logic Low and pull up the voltage level on the terminal F′ to the logic High. The voltage level on the terminal Q′ stays at the logic High, which keeps the transistor 411 turned on so that the voltage level on the terminal F is at the logic Low. This circuit has an advantage in that it operates at a relatively high speed and does not consume DC power. However, there are so many serially connected elements in the NMOS differential logic tree 44 that the current path is relatively long. This will deteriorate the operation speed and elongate the fall time of the output signal if there are a large number of input signals.
FIG. 5 is a diagram showing a logic circuit using a current latch sense amplifier disclosed in U.S. Pat. No. 3,879,621. It includes four P-type transistors 511, 512, 521 and 522, and five N-type transistors 531, 532, 541, 542 and 55. The transistors 511 and 512 are connected in parallel and have gates respectively coupled to receive a clock signal p and an output terminal OUT. The transistors 521 and 522 are connected in parallel and have gates respectively coupled to receive a clock signal φ and an output terminal OUT′. The transistors 531 and 532 have gates respectively coupled to the terminal OUT and OUT′. The transistors 541 and 542 have gates respectively coupled to receive an input signal IN and its inverted signal IN′. The gate of the transistor 55 is coupled to receive the clock signal φ. When the clock signal p is at the logic Low, the P-type transistors 511 and 522 are turned on, the N-type transistor 55 is turned off, the voltage level on the terminals OUT and OUT′ is at the logic High, the transistors 512 and 521 are turned off, the transistors 531 and 532 are turned on, and the drains of the transistors 541 and 542 are coupled to the terminals OUT and OUT′ to receive the logic High voltage thereon. When the clock signal φ is at the logic High, the transistors 511 and 522 are turned off and the transistor 55 is turned on. If the signal IN carries the logic High, the transistor 541 is turned on and the transistor 542 is turned off. A current path from the terminal OUT′ to the ground is generated so that the voltage level on the terminal OUT′ is pulled down. This gradually turns off the transistor 532 and turns on the transistor 531. The voltage level on the terminal OUT is also gradually pulled up to the logic High, which further helps to turn off the transistor 512 and turn on the transistor 531. Finally, the voltage levels on the terminals OUT and OUT′ respectively reach the logic High and Low. Similarly, the voltage levels on the terminals OUT and OUT′ respectively reach the logic Low and High If the signal IN carries the logic Low. Thus, the signal IN is amplified by the current latch sense amplifier.
FIG. 6 is a diagram showing a conventional threshold logic gate circuit. It includes two inverters 631 and 632, four P-type transistors 611, 612, 621 and 622, six N-type transistors 641, 642, 671 and 672, and a NMOS logic circuit 68. The transistors 611 and 612 are connected in parallel and have gates respectively coupled to receive a clock signal φ and the inverter 632. The transistors 521 and 522 are connected in parallel and have gates respectively 20′ coupled to receive the clock signal φ and the inverter 631. The transistors 671 and 672 have gates respectively coupled to the inverters 632 and 631. The transistors 641 and 642 have gates commonly coupled to receive the clock signal φ. The NMOS logic circuit 68 includes (n+1) N-type transistors 651˜65n+1 connected in parallel and having gates respectively coupled to receive n input signals Vx1˜Vxn and the logic High voltage, and (n+1) N-type transistors 661˜66n+1 connected in parallel and having gates respectively coupled to receive n input signals Vy1˜Vyn and the logic Low voltage. The circuit operates in a pre-charge period when the clock signal φ is at the logic Low and operates in an evaluation period when the clock signal φ is at the logic High. At the beginning of the evaluation period, there are multiple current paths from the terminals Q and Q′ to the ground formed by the turned-on transistors on two sides of the NMOS logic circuit 68 so that the voltage levels on the terminals Q and Q′ are pulled down. The total current flowing through the current paths formed by the transistors on one side of the NMOS logic circuit will be larger than the other. This results in one of the voltages on the drains of the transistors 641 and 642 being pulled down faster than the other. For example, the voltage on the drain of the transistors 641 is pulled down faster than that on the drain of the transistors 642. The transistors 621 and 671 are more conductive than the transistors 612 and 672, which reversely pulls up the voltage on the drain of the transistor 642 and helps to pull down the voltage on the drain of the transistor 641. Finally, the voltage levels on the terminals Q and Q′ respectively reach the logic High and Low. The sizes of the transistors in the NMOS logic circuit 68 determine the magnitudes of the currents flowing through the current paths and a logic function between the input signals Vx1˜Vxn, and Vy1˜Vyn, and the output signals on the terminals Q and Q′. However, this circuit only operates as limited logic functions.